Day 1

March 20 




Day 2

March 21


  8:00 -            Registration and Breakfast

  8:45 -  9:00  Welcome

  9:00 -10:00  Keynote I  "EEMBC and the Purposes of Embedded Processor Benchmarking"

10:00 -10:30  Break

10:30 -12:00  Paper session 1

12:00 -  1:30  Lunch

  1:30 -  3:00  Paper session 2

  3:00 -  3:30  Break

  3:30 -  5:00  Paper session 3

  5:00 -  6:30  Panel Discussion  "Architectures for the Future"

  6:30 -            Reception

Day 3

March 22


  8:00 -            Registration and Breakfast

  9:00 -10:00  Keynote II  "Insight, not (random) numbers"

10:00 -10:30  Break

Room A Room B

10:30 -12:00  Paper session 4 

12:00 -  1:30  Lunch

  1:30 -  3:00  Paper session 6 

  3:00 -  3:30  Break

  3:30 -  5:00  Paper session 8 

10:30 -12:00  Paper session 5 

12:00 -  1:30  Lunch

  1:30 -  3:00  Paper session 7 

  3:00 -  3:30  Break

  3:30 -  5:00  Paper session 9 



Day 1 - March 20 (Sunday)




Day 2 - March 21 (Monday)


    8:00 -                 Registration and Breakfast

    8:45 -   9:00      Welcome 

    9:00 - 10:00     Keynote I   ( Markus Levy, EEMBC )                               


10:00 - 10:30     Break


10:30 - 12:00     Session 1: Benchmarking

                             (Chair: David Kaeli, Northeastern University)

12:00 - 1:30     Lunch


  1:30 - 3:00     Session 2: Power and thermal management

                           (Chair: Jim Bondi, Texas Instruments)

  3:00 - 3:30     Break


  3:30 - 5:00     Session 3: Accelerating Simulation

                           (Chair: Sangyeun Cho, University of Pittsburgh)

5:00 - 6:30     Panel Discussion


Doug Burger, The University of Texas at Austin      [ PDF ]
Roy Ju, Intel        [ PDF ]
Ravi Nair, IBM T.J. Watson Research Center        [ PDF ]
Kunle Olukotun, Stanford University         [ PDF ]
Eric Rotenberg, North Carolina State University       [ PDF ]


Erik Altman, IBM T. J. Watson Research Center       [ PDF ]

6:30 -           Reception


Day 3 - March 22 (Tuesday)


    8:00 -                 Registration and Breakfast

    9:00 - 10:00     Keynote II ( Tom Conte, North Carolina State University )                               


 10:00 - 10:30     Break

<<Parallel Session >>


 10:30 - 12:00     Session 4: Multithreading

                               (Chair: David Christie, AMD)

 10:30 - 12:00    Session 5: Statistical and trace-driven simulation

                          (Chair: Charles Lefurgy, IBM)

12:00 - 1:30     Lunch


<<Parallel Session >>


 1:30 - 3:00    Session 6: Data parallel processing

                          (Chair: Lieven Eeckhout, Ghent University, Belgium)

  1:30 - 3:00    Session 7: Network processing

                          (Chair: Rema Hariharan, Sun Microsystems)

3:00 - 3:30     Break

<<Parallel Session >>


  3:30 - 5:00     Session 8: Performance and workload characterization

                         (Chair: David Albonesi, Cornell University)

3:30 - 5:00     Session 9: Communication and reliability

                         (Chair: David Murrell, IBM)

Keynote I 


Embedded processor benchmarking serves many purposes, from providing a framework to guide architectural choices in the development stage to giving original equipment manufacturers an objective means of predicting processor performance in specific application scenarios. Creating embedded processor benchmarks is a comparatively simple task. More difficult is winning acceptance from the diverse audiences who could be expected to rely on them. The Embedded Microprocessor Consortium (EEMBC), now in its seventh year, represents a model that has succeeded relatively well in both tasks. In this presentation, I will describe the structure of EEMBC in its technical and political aspects, review its accomplishments since 1997 in developing various benchmark suites, and discuss the application of various metrics (such as architectural efficiency, power consumption, bus speed, and cache size) beyond raw performance in evaluating the suitability of a given processor for a particular application or system. 


Biographical sketch 

Markus Levy is founder and president of EEMBC, the Embedded Microprocessor Benchmark Consortium. Markus has more than nine years of experience working with EDN Magazine and Instat/MDR, and is a very seasoned editor and analyst with a proven record of processor and development tool analysis, article writing, and the delivery of countless technical seminars. Beginning in 1987, Markus worked for Intel Corporation as both a senior applications engineer and customer training specialist for Intel's microprocessor and flash memory products. While at Intel, Markus received several patents for his ideas related to flash memory architecture and usage as a disk drive alternative. Markus is also co-author of "Designing with Flash Memory", the only technical book on this subject. 

Keynote II 


Hamming said "The purpose of computing is insight, not numbers," yet  this conference, like many today, is awash only in numbers. These numbers are perhaps more strategic than insightful. The numbers are used by designers, who want to prove their invention is better than the status quo. Then there are marketers, who want to prove their product's the one to buy over the competition. And then there are the users, who quite frankly are not getting much insight out of any of this. This talk will step back and discuss two aspects of insightful computing: who speaks for the users, and how much we should trust our numbers.


Biographical sketch

Tom Conte is Professor of Electrical and Computer Engineering and Director, Center for Embedded Systems Research, at North Carolina State University. His research is in the areas of microprocessor architecture, compiler code generation/optimization, and performance evaluation. Conte is the chair of the IEEE Computer Society Technical Committee on Microprogramming and Microarchitecture (TC-uARCH) and a Fellow of the IEEE. He received his Ph.D. degree in EE from the University of Illinois at Urbana-Champaign in 1992.

Panel discussion

More than a decade ago claims were made that "Architecture is dead." Since then we have gone through several Moore's Law generations, and a variety of new ISA proposals and implementations (e.g. Itanium, Java, Niagara, TRIPS, Slipstream) and ISA extensions, particularly for SIMD. What does the future hold? 

The panelists will debate each other and the audience about these and related issues.















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