ADVANCE PROGRAM

Day 1 - March 20 (Sunday)

• WORKSHOP on UNIQUE CHIPS and SYSTEMS (UCAS-1) 

Day 2 - March 21 (Monday)

    8:00 -                 Registration and Breakfast

    8:45 -   9:00      Welcome 

    9:00 - 10:00     Keynote I   ( Markus Levy, EEMBC )                               

• Title: EEMBC and the Purposes of Embedded Processor Benchmarking [ PDF ]

10:00 - 10:30     Break

10:30 - 12:00     Session 1: Benchmarking

                             (Chair: David Kaeli, Northeastern University)

• BioBench: A Benchmark Suite of Bioinformatics Applications,
  Kursad Albayraktaroglu, Aamer Jaleel, Xue Wu, Manoj Franklin, Bruce Jacob, Chau-Wen Tseng, Donald Yeung
  University of Maryland, College Park
  

• Measuring Program Similarity: Experiments with SPEC CPU Benchmark Suites,
  Aashish Phansalkar, Ajay Joshi, Lieven Eeckhout (Ghent), Lizy K. John
  The University of Texas at Austin
  

• Simulation Differences Between Academia and Industry: A Branch Prediction Case Study,
  Gabriel H. Loh
  Georgia Institute of Technology
  

12:00 - 1:30     Lunch

  1:30 - 3:00     Session 2: Power and thermal management

                           (Chair: Jim Bondi, Texas Instruments)

• PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application Specific Instruction Set Synthesis,
  Allen C. Cheng, Gary S. Tyson (Florida State), Trevor N. Mudge
  The University of Michigan
  

• A High Performance, Energy Efficient GALS Processor Microarchitecture with Reduced Implementation, Complexity,
  YongKang Zhu, David H. Albonesi (Cornell), Alper Buyuktosunoglu (IBM T.J. Watson)
  University of Rochester
  

• Studying Thermal Management for Graphics-Processor Architectures,
  Jeremy W. Sheaffer, Kevin Skadron, David P. Luebke
  The University of Virginia

  3:00 - 3:30     Break

  3:30 - 5:00     Session 3: Accelerating Simulation

                           (Chair: Sangyeun Cho, University of Pittsburgh)

• Accelerating Multiprocessor Simulation with a Memory Timestamp Record,
  Kenneth C. Barr, Heidi Pan, Michael Zhang, Krste Asanovíc
  MIT
  

• Intrinsic Checkpointing: A Methodology for Decreasing Simulation Time Through Binary Modification,
  Jeff Ringenberg, Chris Pelosi, David Oehmke, Trevor Mudge 
  The University of Michigan
  

• Enhancing Multiprocessor Architecture Simulation Speed Using Matched-Pair Comparison,
  Magnus Ekman, Per Stenstrom
  Chalmers University of Technology
  

5:00 - 6:30     Panel Discussion

• Topic: Architectures for the Future

Panelists:

Doug Burger, The University of Texas at Austin      [ PDF ]
Roy Ju, Intel        [ PDF ]
Ravi Nair, IBM T.J. Watson Research Center        [ PDF ]
Kunle Olukotun, Stanford University         [ PDF ]
Eric Rotenberg, North Carolina State University       [ PDF ]

Moderator:

Erik Altman, IBM T. J. Watson Research Center       [ PDF ]

6:30 -           Reception

Day 3 - March 22 (Tuesday)

    8:00 -                 Registration and Breakfast

    9:00 - 10:00     Keynote II ( Tom Conte, North Carolina State University )                               

• Title: Insight, not (random) numbers [ PDF ]

 10:00 - 10:30     Break

 10:30 - 12:00     Session 4: Multithreading

                               (Chair: David Christie, AMD)

• Performance Characterization of Java Applications on SMT Processors,
  Wei Huang, Jiang Lin, Zhao Zhang, J. Morris Chang
  Iowa State University
  

• Partitioning Multi-Threaded Processors with a Large Number of Threads,
  Ali El-Moursy, Rajeev Garg, David H. Albonesi (Cornell), Sandhya Dwarkadas
  University of Rochester
  

• Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors,
  Jian Li, José F. Martínez
  Cornell University

 10:30 - 12:00    Session 5: Statistical and trace-driven simulation

                          (Chair: Charles Lefurgy, IBM)

• Motivation for Variable Length Intervals and Hierarchical Phase Behavior,
  Jeremy Lau, Erez Perelman, Greg Hamerly (Baylor), Timothy Sherwood (UC-Santa Barbara), Brad Calder
  University of California, San Diego
  

• Fast, Accurate Microarchitecture Simulation Using Statistical Phase Detection,
  Ram Srinivasan, Jeanine Cook, Shaun Cooper
  New Mexico State University
  

• A Trace-Driven Simulator For Palm OS Devices,
  Hyrum Carroll, J. Kelly Flanagan, Satish Baniya
  Brigham Young University

12:00 - 1:30     Lunch

 1:30 - 3:00    Session 6: Data parallel processing

                          (Chair: Lieven Eeckhout, Ghent University, Belgium)

• On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications,
  Friman Sánchez, Mauricio Alvarez, Esther Salamí, Alex Ramirez, Mateo Valero
  Universitat Politecnicade Catalunya
  

• Dataflow: A Complement to Superscalar,
  Mihai Budiu (Microsoft), Pedro V. Artigas, Seth Copen Goldstein
  Carnegie Mellon University
  

• Scalarization on Short Vector Machines,
  Yuan Zhao, Ken Kennedy
  Rice University

  1:30 - 3:00    Session 7: Network processing

                          (Chair: Rema Hariharan, Sun Microsystems)

• Anatomy and Performance of SSL Processing,
  Li Zhao, Ravi Iyer (Intel), Srihari Makineni (Intel), Laxmi Bhuyan
  University of California, Riverside
  

• Architectural Characterization of Processor Affinity in Network Processing,
  Annie Foong, Jason Fung, Don Newell, Seth Abraham, Peggy Irelan, Alex Lopez-Estrada
  Intel Corporation
  

• Performance Analysis of a New Packet Trace Compressor based on TCP Flow Clustering,
  Raimir Holanda, Javier Verdu, Jorge García, Mateo Valero
  Technical University of Catalonia

3:00 - 3:30     Break

  3:30 - 5:00     Session 8: Performance and workload characterization

                         (Chair: David Albonesi, Cornell University)

• Analysis of Network Processing Workloads,
  Ramaswamy Ramaswamy, Ning Weng, Tilman Wolf
  University of Massachusetts
  

• The Strong Correlation Between Code Signatures and Performance,
  Jeremy Lau, Jack Sampson, Erez Perelman, Greg Hamerly, Brad Calder
  University of California, San Diego
  

• Pro-active Page Replacement for Scientific Applications: A Characterization,
  Murali Vilayannur, Anand Sivasubramaniam, Mahmut Kandemir
  Pennsylvania State University

3:30 - 5:00     Session 9: Communication and reliability

                         (Chair: David Murrell, IBM)

• Reaping the Benefit of Temporal Silence to Improve Communication Performance,
  Kevin M. Lepak, Mikko H. Lipasti
  University of Wisconsin
  

• Balancing Performance and Reliability in the Memory Hierarchy,
  Ghazanfar-Hossein Asadi, Vilas Sridharan, Mehdi B. Tahoori, David Kaeli
  Northeastern University
  

• On the Provision of Prioritization and Soft QoS in Dynamically Reconfigurable Shared Data-Centers over InfiniBand,
  P. Balaji, S. Narravula, K. Vaidyanathan, H.-W. Jin, D. K. Panda
  The Ohio State University

Keynote I 

• EEMBC and the Purposes of Embedded Processor Benchmarking [ PDF ]
  Markus Levy, EEMBC

Abstract

Embedded processor benchmarking serves many purposes, from providing a framework to guide architectural choices in the development stage to giving original equipment manufacturers an objective means of predicting processor performance in specific application scenarios. Creating embedded processor benchmarks is a comparatively simple task. More difficult is winning acceptance from the diverse audiences who could be expected to rely on them. The Embedded Microprocessor Consortium (EEMBC), now in its seventh year, represents a model that has succeeded relatively well in both tasks. In this presentation, I will describe the structure of EEMBC in its technical and political aspects, review its accomplishments since 1997 in developing various benchmark suites, and discuss the application of various metrics (such as architectural efficiency, power consumption, bus speed, and cache size) beyond raw performance in evaluating the suitability of a given processor for a particular application or system. 

 

Biographical sketch 

Markus Levy is founder and president of EEMBC, the Embedded Microprocessor Benchmark Consortium. Markus has more than nine years of experience working with EDN Magazine and Instat/MDR, and is a very seasoned editor and analyst with a proven record of processor and development tool analysis, article writing, and the delivery of countless technical seminars. Beginning in 1987, Markus worked for Intel Corporation as both a senior applications engineer and customer training specialist for Intel's microprocessor and flash memory products. While at Intel, Markus received several patents for his ideas related to flash memory architecture and usage as a disk drive alternative. Markus is also co-author of "Designing with Flash Memory", the only technical book on this subject. 

Keynote II 

• Insight, not (random) numbers [ PDF ]
  Tom Conte, North Carolina State University

Abstract

Hamming said "The purpose of computing is insight, not numbers," yet  this conference, like many today, is awash only in numbers. These numbers are perhaps more strategic than insightful. The numbers are used by designers, who want to prove their invention is better than the status quo. Then there are marketers, who want to prove their product's the one to buy over the competition. And then there are the users, who quite frankly are not getting much insight out of any of this. This talk will step back and discuss two aspects of insightful computing: who speaks for the users, and how much we should trust our numbers.

 

Biographical sketch

Tom Conte is Professor of Electrical and Computer Engineering and Director, Center for Embedded Systems Research, at North Carolina State University. His research is in the areas of microprocessor architecture, compiler code generation/optimization, and performance evaluation. Conte is the chair of the IEEE Computer Society Technical Committee on Microprogramming and Microarchitecture (TC-uARCH) and a Fellow of the IEEE. He received his Ph.D. degree in EE from the University of Illinois at Urbana-Champaign in 1992.

Panel discussion

• Architectures for the Future

More than a decade ago claims were made that "Architecture is dead." Since then we have gone through several Moore's Law generations, and a variety of new ISA proposals and implementations (e.g. Itanium, Java, Niagara, TRIPS, Slipstream) and ISA extensions, particularly for SIMD. What does the future hold? 

• What applications will drive architecture development?

•  Will uniprocessor performance continue to improve?

•  Will most applications move toward multithreaded models to take advantage of SMT and CMP?

•  Are programming models adequate to this task?

•  Are communication and synchronization mechanisms adequate to this task?

•  As more and more function moves on chip, how should the die area be divided between small simple processors, more complex processors, and cache?

The panelists will debate each other and the audience about these and related issues.

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