ADVANCE PROGRAM
April 25 (Wednesday) |
WORKSHOP on UNIQUE CHIPS and SYSTEMS (UCAS-3) |
|
April 26 (Thursday) |
8:00 - Registration 8:45 - 9:00 Welcome 9:00 -10:00 Keynote I (Don Newell, Intel Corporation) 10:00 -10:30 Break 10:30 -12:00 Session 1 12:00 - 1:30 Lunch 1:30 - 3:30 Session 2 3:30 - 4:00 Break |
|
Room A | Room B | |
4:00 - 5:00 Session 3A | 4:00 - 5:00 Session 3B | |
6:00 - Reception (Santa Clara Foyer) | ||
April 27 (Friday) |
8:00 - Registration 9:00 -10:00 Keynote II (Leslie Barnes, AMD) 10:00 -10:30 Break 10:30 -12:00 Session 4 12:00 - 1:30 Lunch |
|
Room A | Room B | |
1:30 - 3:00 Session 5A 3:00 - 3:30 Break 3:30 - 4:30 Session 6A |
1:30 - 3:00 Session 5B 3:00 - 3:30 Break 3:30 - 4:30 Session 6B |
WORKSHOP on UNIQUE CHIPS and SYSTEMS (UCAS-3)
8:00 - Registration
8:45 - 9:00 Welcome
9:00 - 10:00 Keynote I (Don Newell, Intel Corporation)
"Workloads, Scalability, and QoS Considerations in CMP Platforms" ( pdf )
10:00 - 10:30 Break
10:30 - 12:00 Session 1: Simulators/Simulation Methodology
(Chair: Leslie Barnes, Advanced Micro Devices)
Accelerating
Full-System Simulation through Characterizing and Predicting Operating
System Performance,
Seongbeom Kim, Fang Liu, and Yan
Solihin, North Carolina State University, Ravi Iyer and Li Zhao, Intel
Corporation, and William Cohen, Red Hat
A
Comparison of Two Approaches to Parallel Simulation of Multiprocessors,
Andrew Over, Peter Strazdins, and Bill
Clarke, Australian National University
PTLsim:
A Cycle Accurate Full System x86-64 Microarchitectural Simulator,
Matt T. Yourst, State University of New
York at Binghamton
12:00 - 1:30 Lunch
1:30 - 3:30 Session 2: Application Characterization
(Chair: Tao Li, University of Florida)
Understanding
the Memory Performance of Data-Mining Workloads on Small, Medium, and
Large-Scale CMPs Using Hardware-Software Co-simulation,
Wenlong Li, Eric Li, Jiulong Shan,
Yurong Chen, Aamer Jaleel, Qigang Wang, Ravi Iyer, Ramesh Illikkal, Yimin
Zhang, Dong Liu, Michael Liao, Wei Wei, and John Du, Intel Corporation
Characterizing
a Complex J2EE Workload: A Comprehensive Analysis and Opportunities
for Optimizations,
Yefim Shuf, IBM T.J. Watson Research
Center, and Ian M. Steiner, Intel Corporation
Performance
Characterization of Decimal Arithmetic in Commercial Java Workloads,
Mahesh Bhat, John Crawford, Ricardo
Morin, and Kumar Shiv, Intel Corporation
Performance
Impact of Unaligned Memory Operations in SIMD Extensions for Video
CODEC Applications,
Mauricio Alvarez, Esther Salam, Alex
Ramirez, and Mateo Valero, Universitat Politecnica de Catalunya
3:30 - 4:00 Break
|
<<Parallel Session >> |
|
4:00 - 5:00 Session 3A: Simulation Sampling I
(Chair: Ravishankar Iyer, Intel)
Combining
Simulation and Virtualization through Dynamic Sampling,
Ayose Falcon, Paolo Faraboschi, and
Daniel Ortega, HP Labs
Phase-Guided
Small Sample Simulation,
Joshua Kihm, Samuel Strom, and
Daniel A. Connors, University of
Colorado
4:00 - 5:00 Session 3B: Prefetching
(Chair: Mainak Chaudhuri, Indian Institute of Technology, Kanpur)
DRAM-Level
Prefetching for Fully-Buffered DIMM: Design, Performance, and Power Saving,
Jiang Lin, Iowa State University,
Hongzhong Zheng, University of Illinois at Chicago, Zhao Zhang, Iowa State
University, Zhichun Zhu, University of Illinois at Chicago, and Howard
David, Intel Corporation
Last-Touch
Correlated Data Streaming,
Michael Ferdman and Babak Falsafi,
Carnegie Mellon University
6:00 - Reception (Santa Clara Foyer)
8:00 - Registration
9:00 - 10:00 Keynote II ( Leslie Barnes, AMD )
"Performance Modeling and Analysis for AMD's High Performance Microprocessors" ( pdf )
10:00 - 10:30 Break
10:30 - 12:00 Session 4: Performance Models and Phase Classification
(Chair: Nasr Ullah, Freescale Semiconductor)
Using
Model Trees for Computer Architecture Performance Analysis of Software
Applications,
ElMoustapha Ould-Ahmed-Vall, James
Woodlee, Charles Yount, Kshitij A. Doshi, and Seth Abraham, Intel
Corporation
Modeling
and Single-Pass Simulation of CMP Cache Capacity and Accessibility,
Xudong Shi, Feiqi Su, Jih-Kwon Peir, Ye
Xia, and Zhen Yang, University of Florida
Using
Wavelet Domain Workload Execution Characteristics to Improve Accuracy,
Scalability, and Robustness in Program Phase Analysis,
Chang-Burm Cho and Tao Li, University of
Florida
12:00 - 1:30 Lunch
|
<<Parallel Session >> |
|
1:30 - 3:00 Session 5A: Power and Reliability
(Chair: Rajeev Balasubramaniam, University of Utah)
Modeling
and Characterizing Power Variability in Multicore Architectures,
Ke Meng, Frank Huebbers, Russ Joseph,
and Yehea Ismail, Northwestern University
Complete
System Power Estimation: A Trickle-Down Approach Based on Performance
Events,
William Lloyd Bircher and Lizy Kurian
John, University of Texas at Austin
An
Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous
Multithreaded Architectures,
Wangyuan Zhang, Xin Fu, Tao Li, and Jose
Fortes, University of Florida
1:30 - 3:00 Session 5B: Simulation Sampling and Performance Prediction
(Chair: Paolo Faraboschi, HP Labs)
Cross
Binary Simulation Points,
Erez Perelman and Jeremy Lau, University
of California at San Diego, Harish
Patil and Aamer Jaleel, Intel Corporation, Greg
Hamerly, Baylor, and Brad Calder, UC San Diego and Microsoft
Reverse
State Reconstruction for Sampled Microarchitectural Simulation,
Paul D. Bryan, Michael C. Rosier, and
Thomas M. Conte, North Carolina State University
An
Analysis of Performance Interference Effects in Virtual Environments,
Younggyun Koh, Intel Corporation and
Georgia Institute of Technology, Rob Knauerhase, Paul Brett, Mic Bowman,
Intel Corporation, Zhihua Wen, Intel Corporation and Case Western Reserve
University, and Calton Pu, Georgia Institute of Technology
3:00 - 3:30 Break
|
<<Parallel Session >> |
|
3:30 - 4:30 Session 6A: Evaluating Real Systems
(Chair: Russ Joseph, Northwestern University)
Performance
Analysis of Cell Broadband Engine for High Memory Bandwidth Applications,
Daniel Jimenez-Gonzalez, Xavier
Martorell, and Alex Ramirez, UPC-DAC, BSC
Benefits
of I/O Acceleration Technology (I/OAT) in Clusters,
Karthikeyan Vaidyanathan and D. K.
Panda, Ohio State University
3:30 - 4:30 Session 6B: Memory Systems
(Chair: Yefim Shuf, IBM Watson Research Center)
CA-RAM:
A High-Performance Memory Substrate for Search-Intensive Applications,
Sangyeun Cho, Joel R. Martin, Ruibin Xu,
Mohammad H. Hammoud, and Rami Melhem, University of Pittsburgh
Simplifying
Active Memory Clusters by Leveraging Directory Protocol Threads,
Dhiraj D. Kalamkar, Intel Corporation,
Bangalore, Mainak Chaudhuri, Indian Institute of Technology, Kanpur, and
Mark Heinrich, University of Central Florida
Abstract
We have entered the CMP era and are continuously accelerating the pace at which more cores are integrated on the same die. It is now possible to imagine building a 32-core CMP platform in the near future. To make best use of these cores, the workload scenarios are also evolving rapidly. For example, consolidation via virtualization is a rapidly growing phenomenon in the server marketplace. In this talk, we will start by describing our vision of large-scale CMP platforms and future workload scenarios over the next decade. We will then re-visit the typical performance requirements and behavior of these platforms. Based on analysis of several commercial server workloads running individually, we will demonstrate platform scalability considerations. Based on simultaneous execution of heterogeneous workloads, we will show platform quality of service considerations. The intent is to describe the opportunities and challenges that 2015 CMP platforms will face and discuss potential solutions that need further research.
Biographical sketch
Donald Newell is a Sr. Principal Engineer in Intel's Systems Technology Lab. He has spent most of his career working on networking and systems software for server platforms and real-time systems. Don has worked on a number of emerging technologies at Intel. This includes leading the group that developed Intel's frameworks for media streaming over the Internet and to support data broadcast for DTV. Don chaired the Advanced Television System Committee (ATSC) work on data broadcast in DTV and was a co-author of IETF RFC 2429. Don and his group were also key contributors to the recently announced Intel(r) I/O Acceleration Technology (Intel(r) I/OAT). Currently, he leads a group working on Platform QoS with an emphasis on large-scale CMP architectures.
Abstract
This talk will cover performance modeling and analysis at AMD, directed at our X86-64 processor development. Topics covered will include benchmark analysis and workload development for simulation, and simulation tools and methodologies used for power/performance analysis of our next generation of microprocessors.
Biographical sketch
Leslie Barnes joined Advanced Micro Devices in 2001 and manages the Performance and Simulation team for the Sunnyvale Design Center, with responsibilities for the current Athlon64 and Opteron processor modeling and also a new design currently on the drawing boards. Prior to this he worked at HAL computer systems, a Fujitsu Subsidiary, and eventually ended up leading a team building simulators and doing performance analysis for a next-generation Sparc64 based server processor. Leslie has a PhD in Theoretical Chemistry from the University of Western Australia, and has held an NRC Fellowship at NASA Ames Research Center in Mountain View, California, and a Visiting Scientist Fellowship at the IBM Almaden Research Center in San Jose, California.
This website is maintained by ISPASS-2007 Committee.
Contact Byeong Kil Lee, if you have any questions.