FINAL PROGRAM
9:00am - 9:15am Welcome
9 :15am
- 10:15pm Keynote:
"What is the Goal of Computer Architecture
Research?"
Prof. Daniel Jimenez,
UTSA
10:15am - 10:45am Coffee Break
10:45am - 12:00pm Session
I: High Performance Computer Architecture (Session
Chair: )
(25 minutes- regular paper,
15 minutes-WIP)
Integrated Security for System-on-Chip
Architectures
Stanley Bak (University of Illinois -Urbana
Champagne),
Jonathan Heiner (United States Air Force Research Laboratory, AFRL-RI)
Parallelizing Electroencephalogram
Processing on a Many-Core Platform for the
Detection of High Frequency
Oscillations
Gildo Torres (Florida International
University),
Paul McCall (Florida International University),
Chen Liu (Florida International University),
Mercedes Cabrerizo (Florida International University),
Malek Adjouadi (Florida International University)
[WIP] A Study of CUDA Acceleration and
Impact of Data Transfer Overhead in
Heterogeneous Environment
Fahian
Ahmed (Univ of Texas at San Antonio)
Saddam Quirem, (Univ of Texas at San Antonio),
Byeong Kil Lee(Univ of Texas at San Antonio),
Bum Joo Shin (Pusan National University),
Duk Joo Son (ETRI),
Young Choon Woo (ETRI),
Wan Choi (ETRI)
12:00pm - 1:30pm Lunch Break
1:30pm - 2:50pm Session
II: VLSI Design (Session
Chair:
)
(25 minutes- regular paper,
15 minutes-WIP)
The Impact of Technology Scaling in the
SpiNNaker Chip Multiprocessor
Eustace Painkras (University of Manchester),
Steve Furber (University of Manchester)
A Unique Design methodology to generate
reconfigurable Analog ICs with simplified
Design Cycle
Garima
Kapur (Dayalbagh Educational Institute),
S. Mittal (Dayalbagh Educational Institute),
C.M.Markan (Dayalbagh Educational Institute),
V.P.Pyara (Dayalbagh Educational Institute)
An automated design approach of dependable
VLSI using improved canary FF
Ken Yano (Fukuoka University),
Takahito Yoshiki (Fukuoka University),
Takanori Hayashida (Fukuoka University),
Toshinori Sato (Fukuoka University)
2:50pm - 3:20pm Coffee Break
3:20pm - 4:40pm Session
III:
Computer
Architecture (Session
Chair: Prof. Chen Liu,
FIU)
(25 minutes- regular paper,
15 minutes-WIP)
Modified AVR Coding for Test
Data Compression
Sruthi.P.R (Amrita Vishwa Vidyapeetham),
M.Nirmala Devi (Amrita Vishwa Vidyapeetham)
[WIP] A Study on Performance Impact of
Network Delay in Chip Multi Processors
Monobrata Debnath (Univ of Texas at San
Antonio),
Ankil Patel (Univ of Texas at San Antonio),
Byeong Kil Lee (Univ of Texas at San Antonio)
Potential of Dynamic Binary Parallelization
Jing
Yang (University of Virginia),
Kevin Skadron (University of Virginia),
Mary Lou Soffa (University of Virginia),
Kamin Whitehouse (University of Virginia),
[WIP] CRQ-based Fair Scheduling on
Composable Multicore Architectures
Tao Sun (University of Science and
Technology of China),
Hong An (University of Science and Technology of China),
Tao Wang (University of Science and Technology of China),
Haibo Zhang (University of Science and Technology of China),
Gu Liu (University of Science and Technology of China),
Mengjie Mao (University of Science and Technology of China)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Bio:
Dr. Daniel A. Jimenez
is Associate Professor and Chair of the
Department of Computer Science at The
University of Texas at San Antonio. His
research focuses on microarchitecture and
low-level compiler optimizations. Daniel
earned his B.S. (1992) and M.S. (1994) in
Computer Science at The University of Texas
at San Antonio and his Ph.D. (2002) in
Computer Sciences at The University of Texas
at Austin. From 2002 through 2007, Daniel
was an Assistant Professor in the Department
of Computer Science at Rutgers. In 2005
Daniel took sabbatical leave at the
Technical University of Catalonia (UPC) in
Barcelona, Catalonia, Spain. In 2008 he was
promoted to Associate Professor with tenure
at Rutgers. He recently returned from a
second sabbatical leave in Spain at the
Barcelona Supercomputing Center and was
General Chair of the 2011 IEEE HPCA
conference. He is an NSF CAREER award
recipient and ACM Senior Member.
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