Moore’s Law is slowing down and the associated costs are simultaneously increasing. These pressures have given rise to new approaches utilizing advanced packaging and integration such as chiplets, interposers, and 3D stacking. These first generations of architectures can be imagined as small towns or villages of silicon that are assembled together to build a complete processor. So what happens in the future as silicon scaling only gets more challenging and expensive while demand for more compute continues to soar? We envision a future where processors evolve from towns or villages into large-scale silicon “Cityscapes” that aggressively combine high-rise memory stacks, multiple levels and types of compute, smart data movement infrastructure, and more to continue delivering high performance solutions using the full toolbox of packaging and integration options available. However, achieving this future vision of silicon cityscapes will not be without its challenges. We will take a tour of these future cityscapes and explore many of the technical topics that provide rich research opportunities for the community to explore and innovate.
Gabe (he/him) is a Senior Fellow in AMD Research. He received his Ph.D. and M.S. in computer science from Yale University in 2002 and 1999, respectively, and his B.Eng. in electrical engineering from the Cooper Union in 1998. Gabe was also a tenured associate professor in the College of Computing at the Georgia Institute of Technology, a visiting researcher at Microsoft Research, and a senior researcher at Intel Corporation. He is a Fellow of the ACM and IEEE, recipient of ACM SIGARCH's Maurice Wilkes Award, Hall of Fame member for the MICRO, ISCA, and HPCA conferences, and (co-)inventor on over ninety granted US patents.
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