Day 1 -- April 17

Workshops and Tutorials
See the Workshop/Tutorials tab for the full details
08:30 Start morning session
10:00 - 11:00 Coffee
12:00 - 13:30 Lunch (downstairs)
13:30 Start afternoon sessions
15:00 - 15:30 Coffee
17:05 Excursion to the Museum Gustaviaum. Meet on the conference floor.
18:30 Reception in the bar with snacks.

Day 2 -- April 18

08:30 Welcome & Keynote (session chair: Andreas Moshovos)
08:30-08:45 Welcome (General, Program Chairs)
08:45-09:45 Keynote I: Antonio Gonzalez, Director, ARCO Research Group, Cognitive Computers: The Next Wave of Computing Innovation
09:50-11:10 Session I: 3 papers -- Best Paper Candidates (session chair: Sally McKee)
Performance Analysis of Accelerated Biophysically-Meaningful Neuron Simulations,
Georgios Smaragdos (Erasmus Medical Center), Georgios Chatzikostantis, Sofia Nomikou, Dimitrios Rodopoulos (NTUA), Ioannis Sourdis Chalmers University of Technology), Dimitrios Soudris (NTUA), Chris I. De Zeeuw and Christos Strydis (Erasmus Medical Center)
DVFS Performance Prediction for Managed Multithreaded Applications,
Shoaib Akram (Ghent University), Jennifer B. Sartor (Ghent University & Vrije Universiteit Brussel), Lieven Eeckhout (Ghent University)
Addressing Service Interruptions in Memory with Thread-to-Rank Assignment,
Manjunath Shevgoor, Rajeev Balasubramonian (Utah), Niladrish Chatterjee (NVIDIA Research), Jung-Sik Kim (Samsung)
10:50-11:20 Coffee
11:20-12:20 Session II: System and Workload Characterization/Optimizations (session chair: Rajeev Balasubramonian)
Characterization and Bottleneck Analysis of a 64-bit ARMv8 Platform,
Michael Laurenzano (Michigan), Ananta Tiwari, Allyson Cauble-Chantrenne, Adam Jundt, Laura Carrington (EP Analytics),
Analyzing the Energy-Efficiency of Sparse Matrix Multiplication on Heterogeneous Systems: A Comparative Study of GPU, Xeon Phi and FPGA,
Heiner Giefers, Peter Staar, Costas Bekas, Christoph Hagleitner (IBM Research, Zurich)
FastCap: An Efficient and Fair Algorithm for Power Capping in Many-Core Systems,
Yanpei Liu (Facebook Inc., University of Wisconsin Madison), Guilherme Cox (Rutgers University), Qingyuan Deng (Facebook Inc.), Stark C. Draper (University of Toronto), Ricardo Bianchini (Microsoft Research, Rutgers University)
12:20-13:40 Lunch (downstairs)
13:40-14:40 Session III: Reliability (session chair: Pedro Trancoso)
Anatomy of Microarchitecture-Level Reliability Assessment: Throughput and Accuracy,
Athanasios Chatzidimitriou, Dimitris Gizopoulos (University of Athens)
EmerGPU: Understanding and Mitigating Resonance-Induced Voltage Noise in GPU Architectures,
Renji Thomas, Naser Sedaghati, Radu Teodorescu (The Ohio State University)
GUFI: a Framework for GPUs Reliability Assessment,
Sotiris Tselonis, Dimitris Gizopoulos (University of Athens)
14:40-15:10 Coffee Break
15:10-16:10 Session IV: Workloads (session chair: Drew Hilton)
Splash-3: A Properly Synchronized Benchmark Suite for Contemporary Research,
Christos Sakalis, Carl Leonardsson, Stefanos Kaxiras (Uppsala University), Alberto Ros (Universidad de Murcia)
Workload Characterization and Optimization of TPC-H Queries on Apache Spark,
Tatsuhiro Chiba, Tamiya Onodera (IBM Research Tokyo)
Demystifying Cloud Benchmarking,
Tapti Palit, Yongming Shen, Michael Ferdman (Stony Brook University)
Analysis of PARSEC Workload Scalability,
Gabriel Southern, Jose Renau (UC Santa Cruz)
16:10 - 17:00 Session V: poster presentations (5 min each) (session chair: Benjamin Lee)
HL-PCM: MLC PCM Main Memory with Accelerated Read,
Mohammad Arjomand, Amin Jadidi, Mahmut T. Kandemir, Anand Sivasubramaniam, Chita Das, The Pennsylvania State University
Characterization and Architectural Implications of Big Data Workloads,
Wanglei, RenRui, ZhanJianfeng, JiaZhen, ICT,CAS
Elastic Traces for Fast and Accurate System Performance Exploration,
Radhika Jagtap, Andreas Hansson, Stephan Diestelhorst, Radhika Jagtap, Stephan Diestelhorst, ARM Ltd.
CoolSim: Eliminating Traditional Cache Warming with Fast, Virtualized Profiling,
Nikos Nikoleris (Uppsala University), Andreas Sandberg (ARM Research), Erik Hagersten, Trevor E. Carlson (Uppsala University)
Composable Modeling of Coherence and NUMA Effects for Optimizing Thread and Data Placement,
Hao Luo (University of Rochester), Chencheng Ye (Huazhong University of Science and Technology), Pengcheng Li, Chen Ding (University of Rochester)
Characterizing Hadoop Applications on Microservers for Performance and Energy Efficiency Optimizations,
Maria Malik, Avesta Sasan (George Mason University), Rajiv Joshi (IBM T. J. Watson Research Center), Setareh Rafatirad (George Mason University), Houman Homayoun (George Mason University)
RTHpower: Accurate Fine-grained Power Models for Predicting Race-to-halt Effect on Ultra-low Power Embedded Systems,
Vi Tran (UiT The Arctic University of Norway), Brendan Barry (Movidius Ltd., Ireland), Phuong Ha (UiT The Arctic University of Norway)
Agave: a Benchmark Suite Addressing Android System Complexity,
Martin K. Brown, Zachary Yannes (Florida State University, Tallahassee), Mazdak Sanati (Chalmers University of Technology), Michael Lustig (Florida State University, Tallahassee), Alexey Sidelnikov, Sally A. McKee (Chalmers University of Technology), Gary S. Tyson (Florida State University, Tallahassee), Steven K. Reinhardt (AMD)
Storage Consolidation on SSDs: Not always a panacea, but can we ease the pain?
Narges Shahidi, Mohammad Arjomand, Anand Sivasubramaniam, Mahmut Kandemir, Chita Das (The Pennsylvania State University)
17:10 Welcome Reception and Poster Session (banquet room)
18:10-21:00 Banquet
Dinner Keynote
Keynote II: Lieven Eeckhout, Ghent University, Essentially, All Models Are Wrong, but Some Are Useful

Day 3 -- April 19

08:30 Keynote
08:30 Keynote III: Josep Torrellas, University of Illinois Urbana-Champaign, Energy-Efficient Extreme-Scale Manycores
09:30-10:30 Session VI: Understanding CPU and GPU Integration and Systems (session chair: Trevor Carlson)
Observations and Opportunities in Architecting Shared Virtual Memory for Heterogenous Systems,
Jan Vesely (AMD Research/Rutgers University), Arkaprava Basu (AMD Research), Mark Oskin (AMD Research/University of Washington), Gabriel H. Loh (AMD Research), Abhishek Bhattacharjee (Rutgers University), Arkaprava Basu (AMD Research)
Characterizing the Sources of Memory Stalls for Tightly Coupled GPUs,
Johnathan Alsop, Matthew D. Sinclair (University of Illinois at Urbana-Champaign), Rakesh Komuravelli (Qualcomm), Sarita V. Adve (University of Illinois at Urbana-Champaign)
A Comprehensive Performance Analysis of HSA and OpenCL 2.0,
Saoni Mukherjee, Yifan Sun (Northeastern University), Paul Blinzer (AMD), Amir Kavyan Ziabari, David Kaeli (Northeastern University)
10:30-11:00 Coffee Break
11:00-12:20 Session VII: Designs and Design Generators (session chair: David-Black Schaffer)
OpenSoC Fabric: On-Chip Network Generator,
Farzad Fatollahi-Fard, David Donofrio, George Michelogiannakis, John Shalf, George Michelogiannakis (Lawrence Berkeley National Laboratory)
A Study of Mobile Device Utilization
C. Gao, A. Gutierrez, M. Rajan, R. Dreslinski, T. Mudge, C. Wu
Optimizing Rasterizer Performance and Energy in the NyuziProcessor Open Source GPU,
Jeff Bush, Khaled Z. Mahmoud, Mohammad A. Khasawneh, Timothy N. Miller (Binghamton University (SUNY))
AnyCore: A Synthesizable RTL Model for Exploring and Fabricating Adaptive Superscalar Cores,
Rangeen Basu Roy Chowdhury, Anil Kumar Kannepalli, Sungkwan Ku, Eric Rotenberg (North Carolina State University)
Performance Analysis of a Hardware Accelerator of Dependency Management for Task-based Dataflow Programming models,
X. TAN, J. Bosch, D. Jimenez-Gonzalez, C. Alvarez-Martinez, E. Ayguad'e, M. Valero (Barcelona Supercomputing Center, Universitat Politecnica de Catalunya)
12:20-13:40 Lunch
13:40-15:00 Session VIII: Mobile and Cloud (session chair: Radu Theodorescu)
Evaluating Asymmetric Multiprocessing for Mobile Applications,
Songchun Fan, Benjamin C. Lee (Duke University)
MofySim: A Mobile Full System Simulation Framework for Energy Consumption and Performance Analysis,
Minho Ju (Samsung Electronics & Korea Advanced Institute of Science and Technology), Hyeonggyu Kim, Soontae Kim (Korea Advanced Institute of Science and Technology) , Minho Ju (Samsung Electronics & Korea Advanced Institute of Science and Technology)
Mobile Benchmarking Done Right: Understanding the System Impact of Mobile GPUs,
Rene de Jong, Andreas Sandberg (ARM)
X-Mem: A Cross-Platform and Extensible Memory Characterization Tool for the Cloud,
Mark Gottscho (University of California, Los Angeles), Sriram Govindan, Bikash Sharma (Microsoft), Mohammed Shoaib (Microsoft Research), Puneet Gupta (University of California, Los Angeles)
15:00-15:30 Coffee Break
15:30-16:50 Session IX: Tools and Methodologies (session chair: Stefanos Kaxiras)
Interactive Visualization of Cross-Layer Performance Anomalies in Dynamic Task-Parallel Applications and Systems,
Andi Drebes, Antoniu Pop (The University of Manchester), Karine Heydemann (Universite Pierre et Marie Curie / LIP6), Albert Cohen (Ecole Normale Superieure / Inria)
JIT-Assisted Fast-Forward Embedding and Instrumentation to Enable Fast, Accurate, and Agile Simulation,
Berkin Ilbeyi, Christopher Batten (Cornell University)
TaskPoint: Sampled Simulation of Task-Based Programs,
Thomas Grass (Universitat Politicnica de Catalunya and Barcelona Supercomputing Center), Alejandro Rico (ARM), Marc Casas (Barcelona Supercomputing Center), Miquel Moreto (Universitat Politicnica de Catalunya and Barcelona Supercomputing Center), Eduard Ayguad'e (Universitat Politicnica de Catalunya and Barcelona Supercomputing Center)
An Automated Framework for Characterizing and Subsetting GPGPU Workloads,
Vignesh Adhinarayanan, Wu-chun Feng (Virginia Tech)
16:50 Closing
Keynote I
Antonio Gonzalez, Director, ARCO Research Group, Cognitive Computers: The Next Wave of Computing Innovation

A new generation of computing devices is emerging. We envision a world where computing will expand from business and personal uses to be present everywhere: in our cars, in the lighting system of a city, in our shoes, and in the clothes we wear just to name a few. These devices will consist of multiple computing elements, with a few being general purpose but many of them will be specialized in certain computing domains. They will be interconnected and interoperable to leverage their specialization and the complementary information that each one will gather. A key feature of many of these devices will be their ability to understand the world around them and provide real time responses in complex situations, emulating human perception and problem solving. In this talk we will discuss this trend and some of the research areas that will be key to make this vision happen.

Bio: Antonio Gonzalez received his Ph.D. degree from the Universitat Politecnica de Catalunya (UPC), in Barcelona, Spain, in 1989. He joined the faculty of the Computer Architecture Department of UPC in 1986 and became a Full Professor in 2002. He was the founding director of the Intel Barcelona Research Center from 2002 to 2014.

His research has focused on computer architecture. In this area, Antonio holds over 40 patents, has published over 300 research papers and has given over 100 invited talks. He has also made multiple contributions to the design of the architecture of several Intel processors.

Antonio has been program chair for ICS 2003, ISPASS 2003, MICRO 2004, HPCA 2008 and ISCA 2011, and general chair for MICRO 2008 and HPCA 2016 among other symposia. He has served on the program committees for over 100 international symposia in the field of computer architecture, and as an Associate Editor of the IEEE Transactions on Computers, IEEE Transactions on Parallel and Distributed Systems, IEEE Computer Architecture Letters, ACM Transactions on Architecture and Code Optimization, ACM Transactions on Parallel Computing, and Journal of Embedded Computing.

Antonio’s awards include the award to the best student in computer engineering in Spain graduating in 1986, the 2001 Rosina Ribalta award as the advisor of the best PhD project in Information Technology and Communications, the 2008 Duran Farrell award for research in technology, the 2009 Aritmel National Award of Informatics to the Computer Engineer of the Year, the 2013 King James I award for his contributions in research on new technologies, and the 2014 ICREA Academia Award. He is an IEEE Fellow.

Keynote II
Lieven Eeckhout, Ghent University, Essentially, All Models Are Wrong, but Some Are Useful

Performance analysis and modeling is of critical importance to computer systems and architecture research and development. We must design and build our simulators, benchmarks, and analysis tools correctly, and we must measure and analyze our results rigorously, otherwise experimental research and development may lead to incorrect and misleading conclusions and ineffective optimizations. These tools are critical to our understanding of both the problems and the solutions. In this talk, I will revisit the importance of rigorous performance evaluation, and decompose the performance evaluation challenge into two sub-problems, experimental design and data analysis. I will discuss some of the (not so obvious) pitfalls in both experimental design and data analysis, and argue for potential solutions. Along the way, I will remind ourselves why we are doing performance analysis in the first place.

Bio: Lieven Eeckhout is a Professor at Ghent University, Belgium, where he is currently leading a research group with 7 PhD students and 2 postdoctoral researchers. He received his PhD in Computer Science and Engineering from Ghent University in 2002, and he has over 15 years of academic experience in computer architecture research, with a specific emphasis on performance evaluation and modeling. He published more than 150 papers at premier and high-quality venues in the field. His work was awarded with two IEEE Micro Top Pick selections (2007 and 2010); the ISPASS 2013 Best Paper Award; and Best Paper Nominations at PACT 2004, and ISPASS 2012 through 2016. He served as program chair for HPCA 2015, CGO 2013 and ISPASS 2009, and general chair for ISPASS 2010. He is the current editor-in-chief of IEEE Micro (as of Jan 2015), and associate editor of IEEE Computer Architecture Letters, IEEE Transactions on Computers, and ACM Transactions on Architecture and Code Optimization.

Keynote III
Josep Torrellas, University of Illinois Urbana-Champaign, Energy-Efficient Extreme-Scale Manycores

As transistor sizes continue to scale, we are about to witness stunning levels of chip integration, with 1,000 cores on a single die, and increasing levels of 3D stacking. In these architectures, energy and power will constrain the designs even more than they do today. In this context, this talk presents some of the technologies that we may need to deploy to provide very high energy efficiency. We will need Voltage-Scalable cores--i.e., flexible cores that can competitively operate both at high and low voltage ranges, unlike existing big-little designs. Extensive power gating will be crucial, likely with the help of non-volatile memory. Further, to avoid energy waste, we will need power-management controllers that use control-theoretic techniques for maximum energy efficiency. New, more energy efficient devices will also gradually replace CMOS as we know it. A combination of all of these techniques--and more--will be needed.

Bio: Josep Torrellas is a Professor of Computer Science and Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. He is a Fellow of IEEE and ACM. He is the Director of the Center for Programmable Extreme-Scale Computing, a center focused on architectures for extreme energy and power efficiency. He was until recently the Director of the Intel-Illinois Parallelism Center (I2PC), a center created by Intel to advance parallel computing. He has made contributions to parallel computer architecture in the areas of shared memory multiprocessor organizations, cache hierarchies and coherence protocols, thread-level speculation, and hardware and software reliability. He received the 2015 IEEE CS Technical Achievement Award.